Microelectronic devices such as semiconductor chips typically require many electrical connections to other electronic components for input and output of signals, power and ground. The electrical contacts provided on a semiconductor chip or other comparable device for this purpose are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an “area array”) or in elongated rows which may extend parallel to and adjacent each edge of the device's front surface, or in the center of the front surface.
Devices such as chips can be physically mounted on a substrate having electrically conductive elements thereon such as electrically conductive vias and traces, with the contacts of the device electrically connected to electrically conductive elements of the substrate. Some such substrates include openings or vias that extend through opposed surfaces of the substrate to provide an electrical interconnection between the chip at or overlying one surface and another chip or electrical device at or overlying the opposed surface. In some such structures, thermal expansion between the material comprising the via and the surrounding material of the substrate itself can lead to a high degree of stress in the substrate.
Although there have been numerous methods and structures advanced to minimize the stress in the substrate, there is a need for improved designs.